The Static Random Access Memory (SRAM) features in quick-write speed, which is normally used as the interface circuit between the processor and memory as well as high-speed buffer memory of the processor. Development of Very Large Scale Integration (VLSI) and increase in clock frequency of the processor has put forward higher requirements for read-write speed of SRAM. As an important part of SRAM, postponement of address decoder accounts for the majority of postponement of SRAM read-write; therefore, SRAM read-write speed and power consumption are closely associated with the performance of address decoder. Design of high-performance address decoder plays an important role in improvement of SRAM read-write speed, and reduction of power consumption.
Conventional address decoder makes use of CMOS technology for design; accompanied by reduction of feature size to the nanometer scale, such problems as gate delay resulted from interconnect parasitic effect and interconnect crosstalk have become more and more serious; working speed of address decoder is confronted with great challenges. On the contrary, the quasi-one-dimension Carbon Nanotube (CNT) is likely to substitute CMOS process owing to such features as ballistic transmission, stable chemical properties and easy regulation of grid voltage. It is applicable to obtain the Carbon Nanotube Field Effect Transistor (CNFET) by using CNTs as conducting channel. According to study of Literature: DENG J, WONG H S P. a Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part I: Model of the Intrinsic Channel Region[J]. IEEE Transactions on Electron Devices, 2007, 54 (12):3186-3194, inter-electrode capacitance of CNFET is only equivalent to 4% MOSFET inter-electrode capacitance. Therefore, the address decoder designed with CNFET is provided with less postponement, which can improve working speed of the address decoder. In the binary logic system, n input address decoders can control read-write of 2n SRAM units in SRAM. However, in the multi-value logic system, n input address decoders can control more SRAM units. For instance, the ternary logic with the minimum base can take the logic value of “0”, “1” and “2”; ternary n input address decoders can control read-write of 3n SRAM units in SRAM, which improve decoding efficiency of the address decoder. The ternary address decoder used to control SRAM units of the same quantity can reduce the number of packaged pins.
On this account, it is of high significance to design a ternary 2-9 line address decoder realized by CNFET, featuring in low power consumption and less postponement.